The present invention relates to a method and/or architecture for memory cell refresh generally and, more particularly, to a method and/or architecture for controlling a memory cell refresh circuit using charge sharing.
Referring to FIG. 1, a conventional four transistor (4T) loadless SRAM cell 10 is shown. The cell 10 generally comprises a transistor 12, a transistor 14, a transistor 16 and a transistor 18. A node N1 is connected between the drain of the transistor 12 and the gate of the transistor 18. A node N2 is connected between the source of the transistor 14 and the gate of the transistor 16. A first bitline BL is connected to the source of the transistor 12. A second bitline BLB is connected to the drain of the transistor 14. Since there are no internal pull-up transistors, if the node N1 or the node N2 is pulled high, the charge will gradually leak away over time. As a result, a refresh is needed.
To achieve the refresh, the local word line bar (LWLB) is pulled down from the supply voltage VCC to the supply voltage VCCxe2x88x92Vtp, where Vtp is a PMOS threshold voltage. This partially turns on the PMOS pass gates in the memory cell. If the bitlines BL and BLB are at the supply voltage VCC when the local wordline bar LWLB is pulled to VCCxe2x88x92Vtp, the high node in the cell is refreshed.
Referring to FIG. 2, a diagram of the circuit 10 illustrating a conventional refresh operation is shown. The pass gate 12 is partially ON, allowing current to pass and refresh the internal node N1. However, during a write operation, one of the bitlines BL and BLB is pulled to ground. Pulling one of the bitlines BL and BLB to ground could destroy the data in a cell 10 that is being refreshed on the same column as the cell being written to.
Referring to FIG. 3, a diagram of the circuit 10 illustrating conventional data destruction is shown. The pass gate 12 is partially ON, allowing current to discharge the high internal node N1, destroying data.
It is generally desirable to provide a method to switch the refresh off during a write. In order to maximize the time the cell is being refreshed, the refresh circuit should be reactivated as quickly as possible.
One aspect of the present invention concerns an apparatus configured to generate a signal used to refresh a memory cell in response to (i) a write signal, (ii) a global wordline signal, (iii) a block select signal, and (iv) one or more supply voltages.
Another aspect of the present invention concerns a method for controlling a refresh operation of a memory cell comprising the steps of (A) detecting when a first cell in a block is being written to and (B) turning off a second cell that is being refreshed when the first cell is written to.
The objects, features and advantages of the present invention include providing a method and/or architecture for controlling a refresh operation of a memory cell that may (i) control a refresh operation of a memory cell, (ii) be turned hard off when another cell in the same block is written to, preventing data corruption, and/or (iii) use charge sharing to quickly re-enter refresh mode on completion of a write.